A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology

Abstract

A considerable disadvantage that comes with the downscaling of the CMOS technology is the ever-increasing susceptibility of Integrated Circuits (ICs) to soft errors. Therefore, the study of the radiation-induced transient faults in combinational logic has become one of the most challenging issues as the absence of appropriate error-protection mechanisms may lead to system malfunctions. This paper presents an efficient and accurate layout-based Soft Error Rate (SER) estimation analysis for ICs in the presence of both single and multiple transient faults, since the latter are more prevalent as technology downscales. The proposed tool, i.e. SER estimator, is based on Monte-Carlo simulations taking into account a detailed grid analysis of the circuit layout for the identification of the vulnerable areas of a circuit and, in addition, temperature as one of the factors that affect the generated pulse width. The widening of the fault pulses due to elevated temperature is reflected in increased SER according to our results. Finally, the comparison between the simulation results for some of the ISCAS'89 benchmark circuits obtained from the proposed framework and the respective ones obtained from SPICE indicates a fairly good correlation.