Abstract
Floating-point fast Fourier transform (FFT) has been widely expected in scientific computing and high-resolution imaging applications due to the wide dynamic range and high processing precision. However, it suffers the high area and power overhead problem in comparison to fixed-point implementations. To address this problem, this paper presents a novel hybrid SDC/SDF architecture for area and power minimization. It minimizes the required arithmetic units and reduces the memory usage significantly in the single-path delay commutator (SDC) part and single-path delay feedback (SDF) part, respectively. By combining both the advantages on arithmetic units reducing and memory usage optimization of these two parts, the minimized total area and power are obtained without any throughput loss. Logic synthesis results in a 65nm CMOS technology show that the power consumption ranges from 35.7mW to 416.8mW for 16- to 1024-point FFTs at 400MHz, and the total hardware overhead is equivalent to 747k NAND2 gates.
Published Version
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