Evaluation of variable precision computing with variable precision FFT implementation on FPGA

Abstract

In the workflow of SKA-SDP (Square Kilometer Array Radio Telescope-Scientific Data Processing), FFT (Fast Fourier Transform) calculation takes a significant proportion of computation overhead. Moreover, FFT computation has to be done within the tight power budget, which existing generic high performance computing architectures cannot meet. To explore power efficiency of FFT computation, this study is designed with initial evaluation of FFT implementation in variable precision on Xilinx ML605 FPGA (field programmable gate array). The FPGA-based implementation of FFT includes a Xilinx IP Core version 7.1, which supports fixed-point and floating-point computation in single precision. The input data width and phase factor width of fixed-point computation can be varied from 8 bits to 34 bits, allowing that calculation accuracy can be adjusted by setting the width. Since single precision is redundant to accuracy requirement of SKA-SDP, fixed-point calculation is designed to emulate single-precision floating point computation. Calculational power dissipation and throughput with different phase factors on FPGA was measured respectively. The final result demonstrates that the implementation on FPGA ensures sufficient precision at a much less power cost compared with floating-point FFT. In other words, this study indicates variable precision computation would be an efficient way to improve power efficiency.