Abstract
This brief presents an energy-efficient high-speed digital-to-analog converter structure that is implemented in a 10-bit 150-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To reduce energy consumption and improve ADC linearity, a segmented prequantize and bypass architecture is proposed to avoid unnecessary switching of high-weight capacitors based on the results of prequantization. To eliminate possible conversion error caused by parasitic capacitance and provide redundancy, two extra capacitors are inserted. A prototype 10-bit 150-MS/s SAR ADC with the proposed architecture is implemented in a standard 65-nm CMOS technology. According to the simulation, the ADC achieves a spurious-free dynamic range of 83.64 dB and an effective number of bits of 9.52 bits with only 1.20 mW power consumption at a 1.2-V supply, resulting in a figure of merit of 10.9 fJ/conversion-step.
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