A highly-linearized ring amplifier with gain offset calibration

Abstract

This paper presents a high-accuracy and highly-linearized self-biased ring amplifier for switched capacitor analog and RF circuits with offset cancellation and common-mode stabilization. The proposed ring amplifier alleviates the accuracy problems of the conventional ring amplifiers by cancelling the offset caused by the charge sharing due to the difference between the auto-zero voltage (V AZ ) and the common-mode voltage (V CM ) while maintaining the benefits of low power, fast slew-based charging and rail-to-tail output swing. Moreover, the proposed architecture also introduces a signal-detection solution to balance the resetting speed and total power consumption for RF design. A prototype ring amplifier was designed and simulated in a 40-nm CMOS technology with a standard 1.1 V supply voltage. The simulated SFDR of the ring amplifier is 84.46dB (100MS/s), 74.12dB (200MS/s) and 61.4dB (300MS/s), respectively, with a total power consumption of 164 μW and a gain error within 1%.