A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps

Abstract

Ring amplifier has been shown as an alternative to an OTA for its low power consumption and large output swing in low-voltage, deep nanoscale CMOS processes. The robustness of the ring amplifier is an important consideration for its application in products. A transient amplification analysis in this paper reveals the difference between the DC gain and the effective gain of the ring amplifier at different output voltages. This non-linear gain error varies with process corner, supply voltage and temperature (PVT) variation. To compensate this gain error, a calibration method is proposed based on the code density analysis of the output data from the back-end stages. Designed in a 1 V 28 nm CMOS process, a prototype SAR assisted pipeline ADC is proposed with a quick-start ring amplifier. The 12-bit ADC achieves 59.3 dB SNDR and 74.4 dB SFDR with a 6 MHz input and a sample rate up to 625 MS/s. The ADC has measured SNDR and SFDR of 57.2 dB and 67.8 dB, respectively, for a Nyquist frequency input and consumes 13.2mW. The measured SNDR and SFDR remains above 53.5 dB and 66.3 dB for a -6dBFs 50 MHz input with supply voltage and temperature variation.