Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation

Abstract

This brief focuses on the robustness of the ring amplifier (RA), an alternative to the operational transconductance amplifier (OTA) in the deep nanoscale CMOS process. The effective gain (EG) of the RA shows diverse characteristics from the DC gain and can be treated as a non-linear gain error (NLGE). The EG shows a notable variation when taking process, supply voltage, and temperature (PVT) into consideration. An improved statistical calibration based on the back-end stage data is proposed to compensate the NLGE. A prototype SAR-assisted pipeline ADC with a quick-start RA is implemented in a 28-nm CMOS process, achieving 60.3 dB SNDR and 76.5 dB SFDR with a 6 MHz input at 625 MS/s. The SNDR and SFDR are 58.6 dB and 70.7 dB with a Nyquist input frequency and consumes 13.2 mW, achieving Walden and Schreier figure-of-merit (FoM) values of 30.4 fJ/conv.-step and 162.2 dB. For a −6 dBFS 50 MHz input, the measured SNDR and SFDR are above 55.5 dB and 68.9 dB with supply voltage and temperature fluctuation.