Abstract
In this paper, two novel architectures for circuit-level implementation of differential phase frequency detector (PFD) have been presented. Proposed in differential and pseudo-differential mode, the designed PFDs demonstrate all advantages of the differential structures. The notable advantages of proposed structures include a wider frequency range of operation and decreased power consumption, along with significantly reduced dead zone. Both of the circuits have been implemented utilizing TSMC 0.18 μm CMOS technology file. Based on the post-layout simulation results provided by HSPICE, the operating frequency of both PFD structures ranges from 50 Hz to 1 GHz. Moreover, the corresponding power consumptions for the proposed differential and pseudo-differential PFDs are 129μw and 107μw, respectively, while the calculated dead zones of these circuits are π/10 and 2π/25.
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