A high-resolution low-power and multi-bit incremental converter with smart-DEM

Abstract

Alessandro.DAmato@ti.comThis paper describes a second-order 3-bit incremental converter, which employs a novel Smart-DEM algorithm to compensate for the mismatch among unity elements of the multi-level digital-to-analog converter. The design, which is fabricated in a mixed 0.18---0.5 $$\upmu$$μm CMOS technology, achieves 16.7-bit resolution over a 5-kHz bandwidth by using 256 clock periods per sample. A single-step chopping technique leads to a residual offset of 9.7 $$\upmu$$μV. The measured power consumption is 280 $$\upmu$$μW and the achieved figure of merit is 174.95 dB.