Abstract
An architecture of SAR ADC called the delta-modulated SAR ADC (DMSAR ADC) is proposed and designed for medical device applications. In the proposed DMSAR ADC, only the voltage difference between two successive samples is resolved to reduce the conversion steps and decrease the power consumption per channel up to 66%. The experimental chip is implemented in 0.18μm CMOS technology. At the digital supply voltage of 1.35V and Vref=1.00V, the measured power consumption per channel is 1.38μW (2.71μW) and the measured SNDR is 56.68dB (53.89 dB) for Fin=10Hz (7kHz). The ENOB is 9.12b and FoM is 39.54fJ/step.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.