An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme

Abstract

An area-efficient CMOS time-to-digital converter (TDC) based on a pulse-shrinking scheme with an improved cyclic delay line is proposed to achieve low thermal sensitivity in this brief. First, by only thermally compensating the pulse-shrinking unit rather than all delay cells, a large number of compensated circuits could be removed to reduce costs, and the thermal sensitivity of the TDC was still greatly reduced. Additionally, based on the improved cyclic delay line with identical logic gates, an undesired shift resolution caused by the mismatch between the inhomogeneous gates can be successfully eliminated, and the effective resolution can be completely determined by the pulse-shrinking unit. The proposed circuit was fabricated in a Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.35- μm CMOS technology and has an extremely small chip area of 0.025 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is much smaller than the 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of its predecessor. The effective resolution is approximately 40 ps/LSB (least significant bit), and the corresponding integral nonlinearity errors are all within ±0.6 LSB. The experimental results show that a ±5.5% resolution variation of the proposed TDC was achieved in a 0 °C-100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C temperature range. The measured power consumption is 1.65 μW at a measurement rate of 10 samples/s.