A high PVT tolerance TDC with symmetrical Vernier delay ring

Abstract

A novel Vernier delay ring (VDR) used in time-to-digital converter (TDC) is presented in this paper. This Vernier delay ring is perfectly symmetrical compared with traditional Vernier ring by introducing a set of buffers and loads. It significantly reduces the affects of circuit parameters on the process, supply voltage and temperature (PVT) variations. This circuit also inherits the merits of the traditional Vernier ring time-to-digital converter (VRTDC), such as high resolution, large detectable rang. The proposed Vernier Delay Ring TDC achieves a 0.004ps/°C temperature coefficient of time resolution in 0.13μm CMOS technology.