Calibration Techniques in ASIC and FPGA Based Time-to-Digital Converters

Abstract

AbstractThe high-resolution time-to-digital converters (TDC) are currently being implemented in ASIC and FPGA technologies. The methods to implement TDC in ASIC and FPGA technologies are: delay line, Vernier oscillator, and multi-phase clock methods. The TDC implementation has challenges due to spread of delays, delay mismatches, unpredictable place, and route (P&R) delays. The calibration is a crucial aspect to realize high-resolution and robust TDC under process, voltage, and temperature (PVT) variations. This paper describes various time interval measurement methods and their calibration techniques. The unique calibration methodology developed using fewer resources for multi-channel TDCs is also described in this paper. The calibration techniques can be used across technologies of implementation. The TDC using Vernier oscillator method in 0.35 µm CMOS technology having least significant bit (LSB) of 127 ps and Xilinx Spartan-3 FPGA having LSB of 110 ps have been implemented. The delay line method having LSB of 72 ps is implemented in Spartan-6 FPGA.KeywordsASICFPGATime-to-digital conversion (TDC)Calibration