Abstract
A fast and accurate time-domain winner-take-all (WTA) circuit has been developed utilizing a ramp-voltage scan technique in an open loop architecture. The circuit identifies the location of the minimum or maximum value of the multiple analog input voltages by hardware parallel computation. The key feature of the circuit is the replacement of the feedback architecture reported in the previous work by an open-loop OR-tree architecture for delay detection. As a result, the problem of multiple winner detection due to the feedback signal delay has been successfully eliminated. Test circuits were fabricated in a 0.6 µm CMOS technology and the concept has been verified by test chip measurements as well as by post-layout extracted circuit simulation. The time resolution of the open-loop OR-tree architecture circuit is 400 ps, which is 9.5 times higher than that of the conventional WTA circuit utilizing a feedback signal through a multiple-input OR to latch the winner.
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