Negative capacitance circuits for process variations compensation and timing yield improvement

Abstract

The continued demand for higher performance in modern microprocessors places strict timing constraints on the high performance modules such as dynamic circuits and register files. In addition, the increased process variations in scaled technologies results in delay variations around its nominal value. This delay variability results in violating the timing constraints, and correspondingly, causes a timing yield loss. In our previous work, new negative capacitance circuits are connected to the highly capacitive nodes to reduce the overall parasitic capacitance at these nodes. This capacitance reduction reduces the circuit mean delay which results in timing yield improvement, which is verified by using post-layout simulations. In this paper, test chip measurements are provided showing that the adoption of the negative capacitance circuit to a 64-input wide dynamic OR gate is capable of improving the timing yield to 100%.