Abstract
This paper proposed a new structure of Dynamic-Logic Phase Detector (PD) and a π detection circuit. A very simple, low power consumption, high maximum operating frequency and high precision PD is presented. In addition the proposed circuit is based on an open loop architecture and solves the blind-zone and dead zone problems of the conventional circuits. Most PDs have a main problem when the phase difference of two inputs is 180°. In this situation, the loop becomes locked in wrong mode. To solve this problem, a π detection circuit is proposed which, generates an error signal to prevent from locking at π phase difference. SPICE simulation results show that, operational frequency range of proposed PD is 1MHz to 8GHz. The circuit has been designed in 0.18µm CMOS technology. The power consumption of circuit is 0.6 mW at highest frequency.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
