A High-Performance and Hardware-Efficient PCIe Transmission for a Multi-Channel Video Using Command Caching and Dynamic Splicing on FPGA

Abstract

With the increasing requirements of transmitting larger amounts of diverse video and image data, the PCI express (PCIe) interface has been extensively used in high-speed digital systems for multimedia processing and communication. However, the existing PCIe transmission methods are not efficient to transmit multi-channel videos on FPGA processors, as they waste PCIe bandwidth and hardware resources. In this paper, an efficient PCIe transmission method for multi-channel video is presented on an FPGA processor. First, to reduce the programmed I/O (PIO) write latency, the command caching method is adopted. The traditional DMA descriptors are transformed into DMA commands, which are smaller, and the command buffer is used to store these commands. Second, a dynamic splicing mechanism is proposed for data transmission and commands the scheduling separately. The multi-type data is transmitted concurrently in this dynamic splicing mechanism. Moreover, the adjacent commands are spliced into one command, which reduces the DMA initiation times. Finally, the direct kernel memory access technique and timer self-feedback monitor technique are applied to improve the transmission efficiency and enhance the system reliability. The experimental results show that the transmission efficiency of the proposed method is increased by nearly 30% compared with other conventional methods, and the highest measured transfer rate is 1631 Mbytes/s on write and 1582 Mbytes/s on read, which reaches 84.4% of the theoretical maximum.