Research on FPGA timing optimization methods with large on-chip memory resource utilization in PCIe DMA

Abstract

As a high speed serial communication protocol, PCI Express (PCIe) is widely used in data transmission. This paper realized direct memory access (DMA) transmission in PCIe Gen2 8× mode based on Kintex-7 FPGA, and mainly solved timing problems caused by on-chip data stream buffer with large capacity. Firstly, PCIe DMA control process is optimized. Secondly, the connection of FIFO and PCIe IP core is designed to realize DMA data stream transmission. Thirdly, two timing optimization method is proposed to solve the timing risks in FIFO internal delay path and FIFO rd_en control signal respectively. The first method connect various types of FIFO with pipelines. The second method uses a transmission waiting mechanism. Finally, 3.5MB data stream FIFO (90% FPGA memory utilization rate) can be realized without timing failing path in PCIe DMA transmission. The work of this paper has been successfully used in a wide-band direct sampling radar system.