Abstract
An analytical methodology for failure localization inside logical integrated circuits (ICs) based on an electron beam tester is presented. It consists of the splitting of every objective into simpler ones associated with a rigorous choice of the observation technique and of the applied electrical sequences. The choice depends on the IC, the physical parasitic phenomena and the wished goal. The efficiency and the quickness of the methodology is demonstrated by a real case analysis.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
