A Gated-Oscillator based Burst-Mode Clock and Data Recovery (CDR) Circuit

Abstract

This paper describes the detailed design considerations and verification of a 2.35-Gbps burst-mode clock and data recovery circuit. This CDR circuit utilizes a gated-oscillator clock recovery technique with an additional phase locked frequency acquisition circuit which enables it to lock to incoming random data within one or two bits. The CDR circuit was fabricated in 0.18 mum CMOS technology. The active chip area is 0.8times0.8 mm2 and it consumes a total power of 130 mW from a single 1.8 V supply.