A fully integrated VLSI architecture using chaotic PWM for RF transmitter design with electromagnetic interference reduction

Abstract

In recent days, Radio Frequency (RF) transmitter plays an important role in the Wireless Sensor Network (WSN). This transmitter uses Pulse Width Modulation (PWM) approach due to its lower power requirement. But, it is the major source of Electromagnetic Interference (EMI) because of its carrier frequency harmonics. In this work, a new RF transmitter is proposed using a chaotic sequence generator and modulation process for the reduction of EMI. The proposed chaotic sequence generator consumes less area and minimizes the hysteresis on the output signal. Furthermore, a Voltage-controlled Oscillator (VCO) with transmission gate tuning logic is proposed to control the oscillating frequency of VCO during RF carrier wave generation. The proposed VCO allows full swing among power rails by consuming less area and power. The proposed RF transmitter is simulated in Xilinx and LTspice working platforms by considering 0.18 μm CMOS process. The simulation results show that the peak EMI of the proposed RF transmitter is reduced to 39.52 dB μV, which is 10.56 dB less than that of the standard mode design. Furthermore, the proposed RF transmitter consumes only 0.475 mW power to transmit the RF signal.