CMOS-Based Chaotic PWM Generator for EMI Reduction

Abstract

The carrier frequency harmonics and significant high-frequency energy of electromagnetic interference (EMI) produced is a major concern in pulse width modulation (PWM) circuit. This paper proposes a chaotic PWM generator for the reduction of EMI. The chaotic CMOS circuit presented is based on a stroboscopic map to realize the chaotic sequence generator, and then, this chaotic frequency generator is used to replace the constant-frequency generator. The main components of the chaotic PWM circuit are chaotic sequence generator for the chaotic triangle waveforms, the chaotic frequency modulation circuit based on one chip. The chaotic PWM generator is fabricated by a 0.35 μ m standard CMOS process. The energy peak of EMC experiment values are all within the limit of CISPR 22. The peak EMI reduction of the proposed chaotic PWM is 12.85 dB. The experiments show the effectiveness of the proposed CMOS chaotic PWM in reducing EMI.