A Fully Integrated SPAD-Based CMOS Data-Receiver With a Sensitivity of −64 dBm at 20 Mb/s

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A fully integrated 0.35- $\boldsymbol {\mu }\text{m}$ CMOS optical data receiver with a 50- $\boldsymbol {\mu }\text{m}$ diameter single-photon avalanche-diode and a cascoded gating circuit enabling a maximum excess bias voltage of 6.6 V (to obtain a high photon detection efficiency) is presented. To optimize the sensitivity in presence of dark counts and after-pulsing a decision threshold of 2–5 photon counts can be selected. For red light (635 nm) and nonreturn-to-zero modulation the sensitivity is −64 dBm for 20 Mb/s with 100 MHz clock frequency and −57 dBm for 50 Mb/s with 250 MHz.