The design and characterization of high photon detection efficiency CMOS single-photon avalanche diode

Abstract

The high photon detection efficiency (PDE) single-photon avalanche diode (SPAD) designed with a low voltage standard 0.18 [Formula: see text]m CMOS process is investigated in detail. The proposed CMOS SPAD is with P+/N-well junction structure, and its multiplication region is surrounded by a virtual guard ring, with which the premature edge avalanche breakdown can be prevented. The analytical and simulation results show that the CMOS SPAD has a uniform electric field distribution in P+/N-well junction, and the breakdown voltage is as low as 8.2 V, the PDE is greater than 40% at the wavelength range of 650–950 nm, at a low excess bias voltage (light intensity is about 0.001 W/cm2), and the peak PDE at 800 nm is about 48%, the relatively low dark count rate (DCR) of 1.4 KHz is obtained.