Abstract
This paper presents a fully digital binary phase-shift-keying (BPSK) demodulator. The proposed system employs a proposed clipper circuit to clamp all peaks of the negative and positive of the received BPSK signal and to generate a synchronous reset signal. The time domain analysis of the voltage clipper shows that the proposed clipper can reduce the output low-to-high and high-to-low times, compared to conventional inverter. This causes two digital signals are generated at the extremum of the modulated BPSK with shrunk pulse widths and removes the need for voltage controlled oscillator (VCO) signal. The proposed BPSK demodulator is designed and post layout simulated in 0.18 μm standard CMOS technology at 10 MHz carrier wave. Monte Carlo's simulation results of the voltage clipper show that the maximum voltage offset never exceed from the nominal value. The proposed demodulator consumes 14 μW using a 1.8 V power supply and occupies 32 × 35 μm2 core area and 500 × 500 μm2 total chip area.
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