A Forward Angle Recoding CORDIC Algorithm and Pipelined Processor Array Structure for Digital Signal Processing

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We propose a forward angle recoding (FAR) algorithm to implement a high performance CORDIC (COordinate Rotation DIgital Computer) based VLSI processor array. With a redundant encoding of the underlying rotation angles, we prove that the number of CORDIC iterations can be reduced by more than 50% using the FAR algorithm. For pipelined computation, this reduction of CORDIC iterations leads to the reduction of the pipelining latency and overall computing time. In order to implement the FAR algorithm, we propose a novel CORDIC control unit architecture. The regularity and simplicity of this architecture makes it suitable for VLSI implementation. Next, the potential digital signal processing applications of a FAR-based CORDIC processor array are discussed. We survey the various CORDIC array processor architectures suitable for the implementation of discrete Fourier transform (DFT), fast Fourier transforms (FFT), chirped Z-transform, orthogonal digital filters, and lattice filters.