Low Power Low Area Implementation of CORDIC Architecture Using Carry Select Adder for Realtime DSP Applications

Abstract

Coordinate Rotation Digital Computer (CORDIC) algorithm is widely used to improve the efficiency of the hardware implementation of the Digital Signal Processing (DSP) algorithms and other mathematical operations. CORDIC based digital signal processing has become an important tool in communications, biomedical, and industrial products. The fundamental downside of the Conventional CORDIC algorithm is that there exists a considerable amount of repetitive iterations which will add up overall delay to the circuit design. In this paper, we propose a CORDIC algorithm, which is based on the reconfigurable CORDIC architectures that can be configured to operate for circular or hyperbolic trajectories in rotation or vectoring-modes and also can perform various trigonometric function (TF) and exponential functions. The calculation is performed either by using rotation mode or vectoring mode. We use Carry Select Adder (CSLA) for extensive reduction of area complication nature over the standard structure for reconfigurable applications. The proposed architecture has reduced power, delay, and area which is very less when compared to the conventional architectures.