Abstract

An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed consists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test (DUT) consists of the “hard core” PowerPC, running the Linux OS and several peripherals implemented in “soft” (programmable) logic. Faults were injected via the Internal Configuration Access Port (ICAP). The experiments performed here demonstrate that the Linux-based system was sensitive to 199,584 or about 1.4 percent of all tested bits. Each sensitive bit in the bit-stream is mapped to the resource and user-module to which it configures. A density metric for comparing the reliability of modules within the system is presented. Using this density metric, we found that the most sensitive user module in the design was the PowerPC's direct connections to the DDR2 memory controller.

Highlights

  • Over the last decade, Linux Operating Systems (OSs) have been used on several space-based computing platforms

  • A reliable Linux OS can be a useful tool on an FPGAembedded system

  • Our test-bed provides an effective platform for fault injection and other useful experiments investigating the low-level details of the Field Programmable Gate Arrays (FPGAs)

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Summary

Introduction

Linux Operating Systems (OSs) have been used on several space-based computing platforms. Understanding each peripheral’s likelihood of causing a kernel failure due to an SEU aids in understanding the reliability of the system and in creating a more reliable system at the lowest cost To gain this understanding, we constructed a test-bed that allows us to simulate SEUs in the FPGA fabric surrounding a “hard core” embedded processor running a Linux kernel using a process known as fault injection [10]. In [17, 18], they present a reliability analysis tool that would perform a static analysis to predict locations of sensitive bits they would perform fault injection based on their predictions They found that their static analyzer could predict the locations of all the sensitive configuration bits in a design mitigated using TMR without being overly pessimistic. It is likely that their techniques could be used to analyze this Linux system but their system is not available to us and direct comparisons between the two approaches cannot be made

Previous Work
System Architecture
Design under test
Description of Fault Injection Experiment
Sensitive Bit Density Metric
Analysis of Results
Findings
Conclusion
Full Text
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