A Fast Transient Response Capacitor-Less LDO with 123 nA Ultra-Low Quiescent Current

Abstract

This paper presents an output capacitor-less, NMOS regulation FET low-dropout regulator (LDO) with fast load transient response in 55 nm CMOS process. The LDO employs a push-pull error amplifier to achieve high slew rate at low quiescent current and a bidirectional dynamic biasing technique to further improve the load transient response, with barely extra quiescent current. The error amplifier includes a common-gate input stage, whose low input resistance improves stability of the LDO over a wide range of load currents. Due to the low output impedance, NMOS regulation FET is used to improve the transient response. The simulated results show that the LDO with a power supply range from 2.5 to 3.6 V achieves a stable 1.2 V output. When the load current changes in the range of 200 μA - 10 mA with a rise time and a fall time of 200 ns, the LDO can settle within 2.7 μs under a quiescent current of 123 nA.