Abstract

A low-dropout regulator (LDR) using an ultra-fast error amplifier (EA) and ultra-fast unity-gain buffer (UGB) is proposed in this paper. By inserting a UGB between the EA and the inverting second stage, the non-dominant poles are pushed to high frequencies to achieve large loading capability and wide loop bandwidth with good stability. High power supply rejection (PSR) up to very high frequencies is hence achieved. Moreover, transient-enhancement techniques employed by the EA and UGB enable very fast load transient responses. The proposed LDR was designed in a 0.13μm mixed-mode CMOS process. Simulation results show that the quiescent current is 4μA and it achieves 7mV voltage dip for a load current step of 400mA with 1ns edge times. The PSR for all load range are better than -28dB at 10MHz and -9dB at 50MHz, respectively.

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