A fast fault injection platform of multiple SEUs for SRAM-based FPGAs

Abstract

In recent years, SRAM-based FPGAs have been applied in space due to its high density and configurability. However, due to its high sensitivity to SEU, it is difficult to be applied in space. With the decrease of the feature sizes, SRAM-based FPGAs are more sensitive to SEU. Therefore, how to evaluate the sensitivity of a design to SEU in FPGA is very important for the application in space. This paper presents a fast fault injection platform for SRAM-based FPGA, which is able to emulate multiple SEUs in SRAM-based FPGA to evaluate the sensitivity of the design in FPGA and repair the accumulated SEUs by fault injection platform itself. Faults are injected through a configuration port ICAP inside the FPGA by modifying the data in the configuration memory. This paper uses the internal injection through ICAP which is faster than external injection. The locations injected are available at every clock in order to speed up. The fault injection module and the user design module are separated through a specific placement to avoid fault injection module injecting itself and leading to failure. We show the sensitivity of ISCAS85 benchmark circuits configured in PFGA and validate the fault injection platform by comparing the error rate and resource utilization.