A family of CMOS latches with 3 stable operating points

Abstract

A new MOSFET latch that possesses three stable operating points is presented. This circuit is the first of its kind that can be fabricated in a standard digital CMOS process with a single supply voltage and differs from a conventional CMOS latch only by the addition of 2 resistors or 2 transistors. An open loop analysis of the new circuit is introduced to examine its performance. Four variations of this circuit are presented. It is shown that this circuit lends itself well for integrated circuit realization of multi-state logic and memory.