Design techniques for a low-power low-cost CMOS A/D converter

Abstract

A 10 bit 200 kHz algorithmic analog-to-digital converter (ADC) was designed to demonstrate design techniques for low-power low-cost CMOS integrated systems. A switched-bias power-reduction technique reduces the total system power by 10%. A layout technique employing extra thin poly-layer lines instead of conventional dummy devices reduces plasma-induced comparator offsets. Based on a standard digital CMOS process with a single poly layer, the ADC adopts metal-to-metal capacitors for internal charge storage. The experimental ADC was fabricated in a 0.6 /spl mu/m single-poly double-metal n-well CMOS technology, and showed a power consumption of 7 mW and a signal-to-noise-and-distortion ratio (SNDR) of 53 dB at the Nyquist sampling rate with a 3.3 V single supply voltage. The measured differential and integral nonlinearities of the prototype are less than /spl plusmn/0.8 and /spl plusmn/1.8 LSB, respectively.