Abstract
A dynamically reconfigurable scheme for video encoder to switch among many different applications is presented. The scheme is suitable for FPGA implementation and conforms to JPEG, MPEG‐1, MPEG‐2, and H.263 standards. The scheme has emerged as an efficient and cost‐effective solution for video compression as a result of innovative design using well‐partitioned algorithms, highly pipelined architecture and coarse‐grain parallelism. The reconfiguration time of the video encoder is less than 320 μs while switching from one standard to another. Although the dynamic reconfiguration scheme is presented for a video encoder, the same design methodology may be applied effectively for any other application.
Highlights
The advent of SRAM-based Field Programmable Gate Arrays (FPGAs) presented a new capability to the electronics community; dynamically reconfigurable hardware or designs that one can reconfigure on the fly
The controller for the encoder is built into the discrete cosine transform and quantization (DCTQ) module and, the size is marginally more than its inverse, inverse quantization (IQ) and inverse discrete cosine transform (IDCT)
An FPGA implementation of a real time video compression scheme that can be dynamically reconfigured from one standard to another using novel features has been presented
Summary
The advent of SRAM-based Field Programmable Gate Arrays (FPGAs) presented a new capability to the electronics community; dynamically reconfigurable hardware or designs that one can reconfigure on the fly. The dynamic reconfiguration is defined as the selective updating of a subsection of an FPGA’s programmable logic and routing resources while the remainder of the device’s programmable resources continue to function without interruption [3] This means that FPGAs are typically reconfigured many times during the normal operation of an application. In reference [10], the system architecture of an adaptive reconfigurable DSP computing engine for numerically intensive front-end audio/video communications is presented These include finite/infinite impulse response filtering, eight point block DCT, etc., but involve highly interconnected networks and, are difficult to implement on FPGAs. The dynamically reconfigurable video encoder presented in this paper uses moderate-sized coarse grain configuration with very little change in interconnection network resulting in simple design and faster performance and thereby eliminating most of the limitations mentioned earlier. The fifth section presents the reconfiguration times achieved, results and discussions followed by conclusions in the sixth section
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