Abstract
A digital phase-locked loop (DPLL) with background supply noise cancellation is presented. By using a digital low-dropout regulator and a supply noise cancellation controller, this DPLL can tolerate a supply noise of 150mV<inf>PP</inf>. The DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.0195mm<sup>2</sup> and the total power consumption is 7.23mW from a supply of 1.1V. The minimum measured supply voltage sensitivity of the digitally-controlled oscillator is less than 0.0261 [%-f<inf>DCO</inf>/%-V<inf>DD</inf>]. With a 100kHz, 150mV<inf>PP</inf> sinusoidal supply noise, the measured rms jitter of the DPLL at 2.4GHz is reduced from 56.38ps to 15.72 ps.
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