A 1.5GHz 890μW digital MDLL with 400fs<inf>rms</inf> integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC

Abstract

Highly digital clock generator architectures, most commonly implemented using digital phase-locked loops (DPLLs), are evolving as the preferred means for synthesizing on-chip clocks. Their main benefits include small area, reduced sensitivity to analog circuit imperfections, and easier scalability to newer processes. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise poses several design challenges. For instance, a lower bandwidth suppresses TDC quantization error but cannot adequately suppress oscillator phase noise and vice versa. Consequently, either a high-resolution TDC or a low-noise oscillator is needed to achieve low jitter at the expense of large power dissipation and area [1]. Jitter is also degraded by supply noise in the oscillator, which often limits the overall jitter performance of a DPLL embedded in a large SoC. A low-dropout regulator is commonly used to shield the oscillator from supply noise at the expense of additional area, power, and voltage headroom [2]. Since the worst-case jitter sensitivity occurs in the vicinity of the DPLL bandwidth, the regulator bandwidth should be many times the DPLL bandwidth [2]. Furthermore, the peaking caused by the limit cycle behavior of the DPLL further exacerbates supply sensitivity.