A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

Abstract

A digital phase-locked loop (DPLL) with the background supply voltage sensitivity minimization is presented. By using a frequency subtractor, a digital supply voltage sensitivity controller can suppress the supply voltage sensitivity of a DPLL. This DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.006 mm2 where the supply voltage sensitivity controller occupies about 20%. The power consumption is 9.34 mW from a supply of 1.1 V wherein the supply voltage sensitivity controller consumes $840~\mu \text{W}$ . The output frequency of the DPLL is 5 GHz with a divider ratio of 64. The minimum measured supply voltage sensitivity is −0.0044 $[\%-{f} _{\mathrm {VCO}}/\%-{V}_{\mathrm {DD}}$ ]. With a 50-mVPP, 100-kHz sinusoidal supply noise, the peak-to-peak jitter is reduced from 41.48 to 23.15 ps, and the rms jitter is reduced from 7.26 to 3.47 ps.