Abstract
A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in 0.18 ㎛ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ㎰ with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ㎰.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
