A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs

Abstract

This paper analyzes the bit conversion errors in high speed SAR ADCs and proposes a design method to minimize their impact on the ADC performance. By removing the SR latch from the output stage of the differential comparator, while using only one comparator output to generate the differential signals for the internal capacitive DAC, sparkle-code errors are avoided, and conversion errors from a previous bit conversion due to memory effects in the SR latch are eliminated.A 10-bit synchronous SAR ADC has been modeled in MAT-LAB and subsequently implemented at the circuit level in a 22nm FD-SOI CMOS technology. The ADC shows a graceful SNDR degradation at increased sampling frequencies, vastly improving the ADC performance compared to when sparkle-code errors, or conversion errors due to an invalid comparator output, are allowed to occur.