The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction

Abstract

This paper proposes a method of correcting the nonlinear parasitic capacitor of the input pair of comparator in successive approximations analog-to-digital converters (SAR ADCs). The correction method is proposed for the conventional binary-weighted capacitor array topology used in most of high resolution and high speed SAR ADCs. The effects of dynamic capacitor mismatch are first analyzed and then two feasible correction schemes are proposed to mitigate the impact of the nonlinear parasitic capacitor of the comparator. To verify the effectiveness of the proposed method, we designed a SAR ADC in a CMOS 40 nm process and characterized the design by intensive post-simulations. With the proposed correction schemes, the SFDR and SNDR of the SAR ADC increase about 7 and 4 dB, respectively, the differential nonlinearity and integral nonlinearity after calibration are improved from 1.00 and 3.81 to 0.67 LSB/0.57 LSB and 1.46 LSB/0.77 LSB, respectively.