A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume

Abstract

Resistive open defects may occur at interconnects among dies in 3D stacked ICs. A defect level monitor is proposed so as for the defects to be detected before they change into a hard open defect that generates logical errors. The changing process of resistive open defects is monitored by means of charge volume injected from the monitor. It is shown by Spice simulation that resistive open defects whose resistance is greater than 2Q can be detected by online tests with the monitor before changing them to hard open defects in the field.