A built-in test circuit for supply current testing of open defects at interconnects in 3D ICs

Abstract

In this paper, a built-in test circuit is proposed to detect and locate open defects occurring at interconnects between dies in a 3D IC by means of the quiescent supply current. In the test circuit, IEEE 1149.1 test architecture is used to provide a test vector to a targeted interconnect. Testability of the testing with the test circuit is evaluated by Spice simulation. The simulation results show us that a hard open defect and a soft open one generating additional delay of 0.58nsec can be detected at a test speed of 100MHz.