Abstract
In this paper we present a current mode structure for Active Pixel Sensor (APS) which is an essential part in fast Smart CMOS Image Sensors (SCIS). Using two diodes (N+/P-Well and P-Well/Deep-N-Well) in parallel like a Pinned Photo-Diode (PPD) improves sensing of optical signal and leads to higher sensitivity than a conventional Photo-Diode (PD). Also integrated signal amplification inside the collection area of the pixel increases the sensitivity of the device due to the amplification in the pixel. The proposed structure with regards to using Deep-N-Well/P-Substrate junction as a guard ring, suppresses the pixel Cross-Talk (CTK) highly. In pixel Delta Reset Sampling (DRS) architecture helps to make feasible on-chip parallel processing. A post layout simulation for test structure of the proposed current mode APS has been considered by standard 0.18µm RF-CMOS technology of TSMC with a 10µm×10µm PD size. Fill factor of each pixel is 24%.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
