A comparison of Si MOSFET and GaAs MESFET enhancement/depletion logic performance

Abstract

The relative merits of Si MOSFET and GaAs MESFET enhancement/depletion (E/D) logic gates are compared for lithographic rules of 1 µm and minimum gate lengths of 0.7 and 1.0 µm, respectively. An analytic description of ring oscillator delays is applied to both cases. Good agreement is obtained with measured results. Our conclusions are that, using V DD = 4 V for Si gates, GaAs logic gates are faster than Si logic gates by a factor of 1.9 and have a power dissipation five times lower. With process refinements to eliminate parasitics and equalize gate lengths, however, the minimum propagation delays will be in the ratio of their respective effective saturated drift velocities. Therefore, other technologies based upon materials with higher effective v sat (such as InP) will have potentially faster circuits. The requirements of VLSI favor complementary instead of E/D logic, and so GaAs MESFET logic is at a disadvantage because of the lack of a complementary configuration. One of the advantages of the Si technology is its ability to use larger voltages and therefore larger noise margins. Maintaining adequate noise margins may be a potential problem for LSI E/D GaAs circuits.