Abstract
In this paper, the impacts of interface traps on tunneling FET (TFET) are examined in terms of different trap energies and distributions, charge neutrality level (CNL), and effects of random trap fluctuation, in comparison with MOSFET. It is found that the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shifts and subthreshold swing (SS) degradation induced by interface traps in TFET and MOSFET have the same trends, but the impacts on I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> are different because of the novel conduction mechanism of TFETs when compared with MOSFETs. Moreover, nTFET is intrinsically more immune (or susceptible) to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift induced by acceptor(or donor-) type interface traps than nMOSFET. Therefore, reducing the potential degradation induced by the interface traps can be achieved by optimizing the position of CNL. The results indicate that nTFET is more immune to the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift than nMOSFET with CNL below a critical energy. In addition, the trap-induced SS degradation of TFET is severer than MOSFET in electrostatics. Moreover, it is found that the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> , and IOFF fluctuations in nMOSFET and nTFET are also dependent on the position of CNL. With CNL below the critical energy, the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> fluctuation and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> fluctuation of nTFET are smaller than those of nMOSFET. The results are helpful for the interface optimization of TFETs.
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