A comparative study of MOS-FET drain current using high-κ gate stack and FinFET

Abstract

Leakage power dissipation is a major concern at ultra deep submicron range below 90 nm technology for MOS transistors than dynamic and short circuit power dissipation. Use of high-κ dielectric instead of conventional gate insulator like silicon dioxide is an alternative approach to reduce drain leakage current to an extent. If we keep on decreasing the feature size, we will acquire more leakage current. In this paper, we will discuss about the remedy to drain leakage current using high-κ gate stack and FinFET technology up to 14 nm feature size. Some interesting results have been presented here using MINIMOS-NT Global TCAD simulation software. Keywords— High-κ dielectric, Gate stack, EOT of MOSFET, Drain leakage current, tunneling, finFET.