Asynchronous fine-grain power-gated logic

Abstract

With the increasing popularity of battery-driven portable electronics, there is a growing demand for low-power circuit designs. In a typical CMOS digital circuit, power dissipation can be categorized into the dynamic power dissipation, leakage power dissipation, and short-circuit power dissipation. While dynamic power dissipation remains to be the most dominant in many digital circuits, leakage power dissipation has become increasingly more significant especially when the fabrication process enters into deep-sub-micro- or nano-meter-scaled ranges. Asynchronous circuits are well-known for their benefits in terms of dynamic power savings, because asynchronous logic does not switch when inactive. Nevertheless, in deep submicron technologies, leakage currents have become an increasing issue, and thus asynchronous circuits need to focus on reducing power consumption. The project proposed method is an innovative way to reduce power consumption by low-power logic family, called asynchronous fine-grain power-gated logic (AFPL). Here the comparison of power consumption of the proposed system with conventional system was also done.