A compact SOI MOS transistor model for distortion analysis

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SOI technology is now emerging as a mature technology applied in the analog IC design, which necessities an accurate model to describe distortion effects. In this paper a compact transistor model is proposed for distortion analysis of fully depleted SOI MOSFET operating in strong inversion regime. In the model, both short channel effects and self-heating effect (unique to SOI due to the buried oxide) are considered. To obtain a concise and accurate model, an approximation method is developed to determine the dominant physical effects in distortion analysis. The model agrees well with the experimental data.