A combination of multiple channels of FPGA based time-to-digital converter for high time precision

Abstract

The full hardware solution introduced in our previous work could implement multi-channel time-to-digital converters (TDCs) in a Xilinx Kintex-7 FPGA with better than 10 ps RMS precision and 710 MHz measurement throughput. Based on these fundamental TDC blocks, we propose a method to improve the time precision further by merging multiple TDC blocks, which is equivalent to increasing the number of TDC bins multiple times. Two merged TDC channels, each with four TDC blocks, are implemented in the Kintex-7 FPGA and the performance is evaluated. For fixed time intervals in the range from 0 to 20 ns, the average RMS precision measured by the two TDC channels reaches 3.1 ps. The test results show that the FPGA based multi-channel TDC system can be flexibly configured as either more TDC channels with a low time precision or fewer TDC channels with a high time precision.