A CMOS switch-capacitor 14-bit 100 Msps pipeline ADC with over 90 dB SFDR

Abstract

This article presents a design of 14-bit 100 Msamples/s pipelined analog-to-digital converter (ADC) implemented in 0.18 µm CMOS. A charge-sharing correction (CSC) is proposed to remove the input-dependent charge-injection, along with a floating-well bulk-driven technique, a fast-settling reference generator and a low-jitter clock circuit, guaranteeing the high dynamic performance of the ADC. A scheme of background calibration minimises the error due to the capacitor mismatch and opamp non-ideality, ensuring the overall linearity. The measured results show that the prototype ADC achieves spurious-free dynamic range (SFDR) of 91 dB, signal-to-noise-and-distortion ratio (SNDR) of 73.1 dB, differential nonlinearity (DNL) of +0.61/−0.57 LSB and integrated nonlinearity (INL) of +1.1/−1.0 LSB at 30 MHz input and maintains over 78 dB SFDR and 65 dB SNDR up to 425 MHz, consuming 223 mW totally.